`timescale 1ns/10ps

module nand_gete (
    A,B,Y
);

input A,B;
output Y;

assign Y=~(A&B);
    
endmodule

module nand_gete_tb;
reg A,B;
wire Y;

nand_gete nand_gate(.A(A),.B(B),.Y(Y));
initial begin
    A<=0;
    B<=0;
    #10
    A<=1;
    B<=0;
    #10
    A<=0;
    B<=1;
    #10
    A<=1;
    B<=1;
    #10
    $stop;    
end
    
endmodule